Abstract: This project presents a high performance sparse matrix-vector multiplication (SpMV) accelerator on the field-programming gate array (FPGA). By exploiting a hardware-friendly storage theme, named as Variable-Bit-Width Coordinate Block similar Compressed distributed Row, the redundant computation and memory accesses are often reduced greatly through the nested block compression and variable-bit-width column-index secret writing schemes. Supported the planned compression theme, a deeply-pipelined SpMV accelerator is enforced on a Xilinx Virtex XC7VX485T FPGA platform, which may handle distributed matrices with absolute size and poorness pattern. Dadda number is one in all the quickest number utilized in several data-processing processors to perform quick arithmetic functions. The most elements of Dadda number area unit full adder and half adder modules that area unit used for playacting the reduction of the partial Merchandise. A full adder is used because the key part within the style of those multipliers to cut back space and delay. In this work, 8-bit DADDA number victimization VBW-CBQCSR theme is enforced. Experimental results show that the projected style will gain less delay and space is additionally less and reduces the power consumption as compared to the previous works.

Keywords: Sparse Matrix Vector Multiplication (SPMV), FPGA, accelerator, VBW-CBQCSR.